Use of one or more clock signals to synchronize events of digital systems is well known. However, due to clock buffer delays, compacitively loaded clock signal lines, and another signal propagation delays, a time difference may be introduced between a rising or falling edge in one part of a system as compared with a corresponding rising or falling edge, respectively, in another part of the same system. This difference is known as clock skew. In order to address the problem of clock skew, others have proposed using a delay-lock loop. For example, a delay-lock loop is used in U.S. Pat. No. 6,289,068 B1 by Hassoun, et al., in order to deskew a clock signal. In Hassoun, et al., a tap of a delay line is selected in order to mitigate against clock skew. However, accurate tap selection is dependent on a phase detector.
Jitter or phase noise is a well-studied phenomenon in circuit implementation. Accordingly, if an input signal, such as a reference clock signal, is provided to a delay-lock loop (“DLL”), jitter associated with such an input signal can introduce uncertainty with respect to such clockage. More particularly, jitter can cause a phase detector to incorrectly detect whether a signal is leading or lagging. This incorrect detection can lead to the selection of an incorrect tap of a delay line for deskewing a clock.
Accordingly, an inaccurate clock deskew may preclude adjusting a clock signal to one period of a desired frequency. Thus, selection of taps may need to be made to provide a clock period which is longer than that desired or latency may be introduced. Moreover, a jitter can cause dither of selection of such taps, thus further destabilizing a digital system. Additionally, jitter caused by a source external to a unit under test, such as a microchip, can cause a passing part to erroneously fail.
Accordingly, it would be both desirable and useful to provide method and apparatus for reducing effect of jitter in order to reduce dither, as well as to enhance accuracy of a DLL.